Verification by Error Modeling: Using Testing Techniques in...

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Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)

Name: Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
ISBN: 9781402076527

Katarzyna Radecka, Zeljko Zilic

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This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

Categories:

Society, Politics & Philosophy - Social Sciences

Year:

2003

Edition:

Publisher:

Oxford University Press

Language:

english

Pages:

233

ISBN 10: